Lumerical Improves Photonic Integrated Circuit Design and Simulation Accuracy with Compact Model Library for imec 50Gb/s Silicon Photonics Process

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Lumerical has developed a compact model library of active and passive photonic elements calibrated to imec’s iSiPP50G silicon photonics process, improving design accuracy and reliability

Vancouver, BC (March 15, 2017)

Lumerical ( announced today the availability of a calibrated compact model library (CML) for imec’s 50Gb/s wafer-scale integrated silicon photonics platform (iSiPP50G) and process design kit (PDK). The Lumerical iSiPP50G CML enables circuit designers to accurately simulate and optimize photonic integrated circuit (PIC) behavior and performance prior to fabrication, reducing costly design errors and enabling first-time-right designs within Lumerical’s PIC simulator, INTERCONNECT.

Silicon photonics is emerging as a leading technology to address the challenges facing today’s rapidly evolving connected world. Driven by ever-increasing demands for high-performance optical communication systems, silicon photonics applications are expanding to include board- and chip-level interconnect, diagnostics and other applications in health-care, environmental sensing, augmented and virtual reality and quantum computing.

The Lumerical iSiPP50G CML enables users to accurately simulate, analyze and optimize designs using INTERCONNECT prior to fabrication and ensures design intent matches physical device operation. INTERCONNECT operates as a standalone schematic design and simulation environment, or integrates into select EDA-centric workflows for complete chip design and layout.

“By combining measured data from multiple imec wafer runs with key operating parameters extracted from our component level simulation tools, we can generate calibrated compact models for each component that chip designers can use to design, simulate, and optimize photonic integrated circuits,” stated Dr. James Pond, CTO at Lumerical. “The models are a critical aspect of PDK driven design, enabling designers to focus on circuit performance rather than component design and to align design intent with fabrication characteristics, reducing design iterations and development costs.”

The iSiPP50G process offered by imec includes active modulators and photodetectors capable of operating reliably at 50Gb/s NRZ. The process is ideally positioned to address the high performance, low power requirements of Nx100Gbs telecom and datacom transceivers, along with low cost, highly integrated sensing and LiDAR applications. The iSiPP50G PDK contains more than 50 active and passive components with corresponding calibrate compact models.

“We are excited about the inclusion of the CML for INTERCONNECT in the iSiPP50G PDK. IMEC aims to provide a robust ecosystem for our users to develop innovative photonic devices and applications,” said Phillip Christie, Leader of the Business & Technology Strategy Group, imec.IC-link. “PDK-driven design methods and processes are critical for silicon photonics to meet the reliability and cost targets needed for widespread commercial adoption, and accurate chip level simulation models are a critical aspect of the PDK offering.”

Be among the first to see a demo of the iSiPP50G CML at OFC 2017 in Los Angeles, California. On March 20th, the hands-on short course: SC454 Silicon Photonic Circuits and Systems Design will feature application examples using INTERCONNECT and the imec iSiPP50G CML. More details regarding the imec PDK offering can be found on the Europractice IC Service website. The first closing date for the next imec iSiPP50G MPW run is May 5, 2017.

To learn more about Lumerical’s interaction with imec and its other foundry partners, visit:

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