Building and Using Statistical Compact Models for Circuit Level Yield Analysis

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More than ever, photonic circuit designers seek to predict the yield of circuits and systems. This requires photonic process design kits (PDKs) equipped with process variability data extracted by foundries, made possible by costly and labor-intensive measurement efforts. For many years, the testing capacity required for this task was out of reach for many photonics foundries. However, with the significant advances in automated testing over the last decade, photonics foundries are now more commonly obtaining this data and the photonics industry is poised to deliver statistical solutions to circuit designers. As a result, PDK designers are faced with the complex challenge of bringing together multiple data sources to generate accurate and process-sensitive compact models, in addition to preparing auxiliary statistical distribution data to enable yield analysis in the photonic circuit simulator.

Geared for photonic PDK developers and circuit/system-level designers, this webinar explains how to create compact models for statistical simulations solely using measurement data and in combination with multiphysics component-level simulations. Additionally, we’ll demonstrate how Ansys tools help automate the compact modeling process, from data collection through to model generation. We will also demonstrate how to run layout-aware yield analysis with the resulting CML.

  • Learn statistical compact modeling and simulation basics.
  • Discover the latest developments on automated workflows for collecting nominal and statistical data for compact models, leveraging a combination of measurement data and component-level simulation.
  • Understand how to use Ansys Lumerical CML Compiler for automated generation of compact models.
  • Explore how to obtain layout-aware circuit yield in Ansys Lumerical INTERCONNECT.

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