Towards Manufacturability with a Statistically-Enabled PDK and Tool Flow, Part 2: Statistical Co-simulation with Cadence Virtuoso

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Photonics is everywhere and design flows continue to mature to meet the cost and scalability demands of manufacturing necessary for broad commercial markets. The introduction of photonic/electronic process design kits (PDKs) in recent years has raised the level of abstraction for photonics design to unprecedented levels of productivity. This has been made possible with the introduction of advanced circuit-level design flows that include Lumerical’s circuit simulation tool INTERCONNECT, industry-standard Cadence Virtuoso electronic/photonic design automation environment, and Lumerical’s cross-simulator compact model library (CML) generation tool CML Compiler. The most recent addition to these flows is the addition of support for statistical PDKs. This has empowered designers to accurately simulate manufacturing variability leading to better yield, a reduced need for costly prototype iterations, reduced manufacturing risk, and ultimately improved return on investment.

This two-part webinar focuses on statistical PDKs and a statistically enabled design and simulation flow with Lumerical’s INTERCONNECT and CML Compiler. For PDK designers, the webinar series will describe a streamlined workflow for adding compact model libraries with statistical support to their PDKs. The webinar shows how circuit-level designers can quickly and efficiently design electronic/photonic circuits with Lumerical INTERCONNECT and Cadence Virtuoso platform. The webinar will include several workflow demonstrations and will feature the currently available statistically enabled AIM PDK.

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