Schematic Driven Simulation and Layout of Complex Photonic ICs


Built around the Virtuoso® custom design platform, an electronic-photonic design environment has been developed, enabling schematic driven design for photonic and electronic circuits, photonic component parameter extraction and model generation, photonic circuit simulation and photonic mask layout implementation for monolithic and hybrid photonic circuits.

The applications space for integrated photonics continues to expand into traditional electronics areas and the transition from research towards commercial product development is intensifying. To support these trends existing domain specific design methodologies have to combine to provide the most efficient and least error prone design environment, enabling reliable analysis, optimization and design of both electronic and photonic circuits. As photonics presents physical and analytical challenges that require unique methods not used in traditional electronic IC design tools [1], these need to be addressed to enable the designer of future complex photonic-electronic ICs with a schematic driven simulation and layout design flow.

 

EPDA Diagram
Figure 1: The developed Electronic/Photonic Design Automation (EPDA) environment. Centered around Cadence’s Virtuoso® custom design platform, enabled by PhoeniX Software’s OptoDesigner and Lumerical’s INTERCONNECT and component-level simulation tools.
Curvilinear layout Parametric analysis
Figure 2: Example of a curvilinear layout. Figure 3: Parametric analysis (unbalance) of MZI modulator.

 

The developed design flow: A comprehensive design environment is being developed in close collaboration between Cadence Design Systems, Lumerical Solutions, Inc., and PhoeniX Software. This work enhances a traditional Electronic Design Automation (EDA) environment with Photonic Design Automation (PDA) capabilities, with the following six key features as depicted above in Figure 1:

  1. Schematic capture of both the photonic and electronic circuits. Today most photonic circuits are relatively simple, i.e. they consist of a small number of photonic building blocks. While for pure photonic circuits a layout driven approach is suitable it becomes too error prone, cumbersome, and disjointed for larger circuits and more importantly when electronic and photonic circuits have to be designed and optimized together it is important to start with a schematic design first.
  2. Photonic/electronic circuit simulation and optimization. Recent work in modelling photonic and electronic systems typically involve Verilog-A behavioral models for photonic components and commercial spice simulators to drive the simulation [2, 3]. This approach becomes challenging as the number of channels and propagating modes are increasing. These limitations are not only arising because of the rapidly increasing number of non-physical connections between components but also because of convergence issues [4]. Another more practical limitation of Verilog A is that the models must be described in the time domain, when most of the multi-mode components are described by frequency-domain s-parameters. The developed EPDA framework uses INTERCONNECT, a dedicated optical circuit simulator, in concert with Spectre® for co-design and co-simulation.
  3. Schematic Driven Layout (SDL). The same ‘golden schematic’ as captured and evaluated in step 1 and 2 is used to drive the layout implementation of the electronic and photonic circuit.
  4. Support for parametrized complex curvilinear shaped components. To overcome grid-based design limitations introducing additional light scattering and cross-talk,.OptoDesigner’s native curvilinear and all angle shape generator acts as the engine within Virtuoso’s® layout environment. This drives the creation of the layouts of the, often highly parametrized and ‘curvy’, photonic components. The same engine is applied to create the connecting waveguides between the components. Special care is taken for proper waveguide stitching to create composite waveguide interconnects by introducing optical ports in Virtuoso®, without the need to write large scripts.
  5. Layout-to-schematic back annotation of device and waveguide parameters for iterative circuit verification and optimization. After the implementation of the circuit’s layout in step 4, the EPDA environment allows designers to re-evaluate the behavior of the circuit, based on the actual implementation of the parametrized components and waveguide interconnects.
  6. Photonic PDK generation. For complex circuits designers need to rely on a schematic-driven design flow enabled by Process Design Kits (PDKs) containing libraries of calibrated and validated compact models for simulation, but also layout and process information, along with the necessary design guidelines and rules. The EPDA framework also enables the automation of 3D-model generation from mask layout for physics based simulations, such as process, optical, thermal, and electro-optical simulations.

References:

  1. Pavesi, Lockwood et. al.; Silicon Photonics III, Systems and Application; p99-p156; Springer 2016.
  2. C. Sorace-Agaskar et al.; Optics Express 23, 27, 180-27, 203 (2015)
  3. K. Zhu et al.; Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium, pp. 615-618
  4. C.C. McAndrew et al.; IEEE Journal of the Electron Devices Society, 3, 383-396 (2015)